• 中断控制器 (UIC) 的中断分配

• 中断向量表

Exception preTx. The setting of IP speciTes whether an exception vector offset is prepended with Fs

or 0s. In the following description,

0 Exceptions are vectored to the physical address 0x00

nnnnn is the offset of the exception vector. See Table 7-1.0n_nnnn

1 Exceptions are vectored to the physical address 0xFF

Fn_nnnn

The reset value of IP is determined by the IIP bit (bit 2) in the hard reset confguration word.

　

    这个表结合地址映射表可知系统复位的地址是 Socket Flash地址+系统复位偏移地址 = 0xFFF80000 + 0x0100 = 0xFFF80100,即系统通电后,跳到0xFFF80100的位置开始执行程序.

MPC860串口中断过程

    MPC860集成了两个处理块,一个处理块是嵌入的PowerPC核，另一个是通信处理模块（CPM）.通信处理模块有4个SCC和2个SMC,这六个通信口可以通过设置来支持多种协议和通信方式,也可设置为串口UART模式(是通过寄存器GSMR或SMCMR),功能和中断的定义和通常的串口定义基本是一致的在寄存器SCCM/SCCE的位14和位15定义了在何种情况下产生硬件中断.

    根据MPC860中SCC UART Event Register(SCCE)的位14和位15定义,位14是数据发送中断标志位,位15是数据接收中断标志位,首先设置SCC UART Mask Register(SCCM)的位14和位15为1,使能接受和发送中断.

如果串口收到数据,则产生硬件RX中断,SCCE为15置1,通知系统有数据到达,有相应的中断例程ISR来取数据.

    发送的情况下,数据FIFO为空,产生TX中断,告诉系统发送准备就绪,可以发送,ISR把数据放入FIFO中,发送中断位清零.当发送完毕后,FIFO再为空,再次产生中断,告诉系统发送准备就绪,继续发送.

MPC860片选信号的编程方法

在MPC860中，有片选信号CS0，CS1，...，CS7对他们的操作主要是要改变片选信号的电平 

一般来说片选信号的发生是对和这一片选线相关联的地址进行操作（读写）时片选信号改变。片选信号通常为低电平有效。比如MPC860的CS0是boot rom，硬件reset后，CPU会从boot rom的起始地址开始执行，CS0变为低
电平。

CS0\ ____                         片选型号
             |
             |____________________
we\ _____                        写有效
              | 
              |_____________________

data _______  __  __                数据信号
                       | | | | | 
                 |_| |_| |

所以只要对一个相应的地址操作，和这个地址芯片（bank)相连的CSx就会改变。
MPC860对CSx分配地址空间的在BRx中定义，BR0,BR1...BR7分别对应8个片选线CS0--CS7。

System Reset Interrupt (0x00100)

A system reset interrupt occurs when IRQ0 is asserted. When the exception is taken, processing begins at offset 0x00100. A hard or soft reset also causes program execution to begin fetching at 0x00100 after the associated reset actions.

Register Setting

SRR0: Set to the (Effective Address) EA of the next instruction of the interrupted process.

SRR1: Saves the machine status prior to exceptions and to restore status when an

1-4 ,-------0

10-15,--- 0

Others Loaded from MSR[16-31]. SRR1[30] is cleared only by loading a zero from MSR[RI].

MSR : IP No change ME No change LE Value of MSR[ILE] of the interrupted process. Others -----0

r f i instruction is executed.

In the MPC860 the external interrupt is generated by the on-chip interrupt controller. It is software acknowledged and maskable by MSR[EE], which hardware clears automatically to disable external interrupts when any exception is taken.

Register Settings after an External Interrupt

Register Setting Description

SRR0 Set to the effective address of the instruction that the processor would have attempted to execute next if no interrupt conditions were present.

SRR1: 0, Loaded with equivalent bits from the MSR

1-4, Cleared; 5-9, Loaded with equivalent bits from the MSR; 10-15, Cleared; 16-31, Loaded with equivalent bits from the MSR

Note that depending on the implementation, reserved bits in the MSR may not be copied to SRR1.

MSR POW 0; ILE --; EE 0; PR 0; FP 0; ME --; SE 0; BE 0; IP --; IR 0; DR 0; RI 0; LE Set to value of ILE

　

Hard Reset ConTguration Word

The hard reset configuration word is sampled from the data bus. These bits determine the default values of the corresponding bits in the SIUMCR, IMMR, and MSR.

IIP

IIP is cleared (default), the MSR[IP] initial value is one; if it is set to one, the MSR[IP] initial value is zero.

ISB

base address of the internal memory space.

00 0x00000000.

01 0x00F00000.

10 0xFF000000.

11 0xFFF00000

:bit 7-8, Initial internal space base select. Defines the initial value of the IMMR bits 0-15 and determines the:bit1: Initial interrupt prefix. Defines the initial value of the MSR[IP] which defines the interrupt table location. If.