<meta name="ProgId" content="Word.document" /> <meta name="Generator" content="Microsoft Word 12" /> <meta name="Originator" content="Microsoft Word 12" /> I’d like to thank Al Crouch for spending last week thoroughly explaining the status of the test readiness for 3D stacks. It’s an extremely complex issue with complex answers. I’ve summarized it here, but recommend you read the whole text for the full picture.  The picture is a bit grave at the moment, and although steps are being made, it’s not likely the test solutions will be ready when the manufacturers start rolling out product.  It’s time to get cracking!.

Q.  Is test an issue with 3D configurations in general (PoP, FO WLP), or just with regard to 3D ICs using TSV interconnects? 

A. The short answer is that the "test access" and "test feature" problem actually exists in SoCs, stacked packages, and 3D ICs using TSV Interconnects -- but the most extreme case is the TSV since they are very expensive in size and number and the goal is to minimize the number used and to actually identify the physical location of the "test vias" passed on to each die.

Q. How do we resolve the question, should we be testing before the bond or after the bond?

A. Test needs to be done both before and after the bond is formed.  Lack of testing at each step of the assembly process can lead to loss of profit margin and a perception by the end customer of a low quality or low reliability.

Q.  How can this be best achieved, based on the delicate nature of the structures?

A. The new 1149.7 Compact JTAG standard should be employed so that all test features can be accessed and operated through a 2-port interface (TMSC and TCKC) and all test data and control are now delivered through a packet protocol. This type of architecture reduces the test interface to 2 pads on each die (and 2 larger dedicated wafer-probe pads can be made on each die to support probe-test) - and test becomes an exercise in touching 2 pads and the powers and grounds needed to provide test power (which also reduces the problem of die failing due to insufficient-contact at probe). When stacked, the 2 Pads can be replaced with TSVs and the testing of the die stack can now be done similarly to wafer-probe, except that the test instruments on multiple die can now be accessed and operated - and simultaneously if necessary.

Q. When the manufacturing companies have the capability to make stacked-die and TSVs in volume, will everything that is needed to conduct test, maintain yield, and achieve high-quality levels be in place?

A. Right now, given what I know, my answer is “NO!"  Right now, the die being delivered are being functionally tested (which slows the progress of getting the final chip into production), or they are no better than blind-assembled chips (none or little testing). If the first markets to use the stacked die in high volume are singing greeting cards which can sustain a fairly low test content, then great, we’re up and running. However, if the first markets to really make use of the stacked die in high volume are the microprocessors and data-processing devices — then test and quality concerns are high, and product introductions and lifetimes are short.